Renesas RL78/G1P Hardware User Manual page 222

RL78/G1P
Figure 6-60. Operation Procedure When Delay Counter Function Is Used
TAU
default
setting
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel Sets the corresponding bit of the noise filter enable
default register 1 (NFEN1) to 0 (off) or 1 (on).
setting
Sets timer mode register mn (TMRmn) (determines
operation mode of channel).
INTTMmn output delay is set to timer data register mn
(TDRmn).
Clears the TOEmn bit to 0 and stops operation of TOmn.
Operation Sets the TSmn bit to 1.
start The TSmn bit automatically returns to 0 because it is a
trigger bit.
The counter starts counting down by the next start trigger
detection.
 Detects the TImn pin input valid edge.
 Sets the TSmn bit to 1 by the software.
During Set value of the TDRmn register can be changed.
operation The TCRmn register can always be read.
The TSRmn register is not used.
Operation The TTmn bit is set to 1.
stop The TTmn bit automatically returns to 0 because it is a
trigger bit.
TAU The TAUmEN bit of the PER0 register is cleared to 0.
stop
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
Hardware Status
Input clock supply for timer array unit 0 is stopped.
(Clock supply is stopped and writing to each register is
disabled.)
Input clock supply for timer array unit 0 is supplied. Each
channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEmn = 1, and the start trigger detection (the valid edge
of the TImn pin input is detected or the TSmn bit is set to
1) wait status is set.
Value of the TDRmn register is loaded to the timer count
register mn (TCRmn).
The counter (TCRmn) counts down. When TCRmn
counts down to 0000H, INTTMmn is output, and counting
stops until the next start trigger detection (the valid edge
of the TImn pin input is detected or the TSmn bit is set to
1).
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
Input clock supply for timer array unit 0 is stopped.
All circuits are initialized and SFR of each channel is
also initialized.
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