Renesas RL78/G1P Hardware User Manual page 410

RL78/G1P
Figure 11-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
Write MDmn0 bit to 1
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 11-68 Timing Chart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode).
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Starting setting
<1>
SAU default setting
Setting
transmission/reception data
Enables interrupt
Wait for transmission
completes
<3><6>
Buffer empty/transfer end interrupt
BFFmn = 1?
Yes
<4>
Read receive data to SIOp
(= SDRmn [7:0])
<7>
Subtract -1 from number of
transmit data
= 0
Number of communication
data?
≥ 2
Yes
Writing transmit data to
SIOp (= SDRmn [7:0])
RETI
No
Number of communication
data = 0?
Yes
Yes
Communication
continued?
No
Disable interrupt (MASK)
<8> Write STmn bit to 1
End of communication
CHAPTER 11 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 11-63.
(Select buffer empty interrupt)
Setting storage area and number of data for transmission/reception
data
(Storage area, Transmission/reception data pointer, Number of
communication data and Communication end flag are optionally set
on the internal RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask
(XXMK) and set interrupt enable (EI)
Start communication when master start
providing the clock
When buffer empty/transfer end is
generated, it moves interrupt
processing routine
No
Other than the first interrupt, read reception data
then writes to storage area, update receive data
pointer
If transmit data is remained, read it from storage area
= 1
and write it to SIOp. Update storage pointer.
If transmit completion (number of communication data
= 1), Change the transmission completion interrupt
<5>
Clear MDmn0 bit to 0
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