Operations Of Clock Output/Buzzer Output Controller; Operation As Output Pin; Cautions Of Clock Output/Buzzer Output Controller - Renesas RL78/G1P Hardware User Manual

RL78/G1P

7.4 Operations of Clock Output/Buzzer Output Controller

One pin can be used to output a clock or buzzer sound.
The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
The PCLBUZ1 pin outputs a clock/buzzer selected by the clock output select register 1 (CKS1).

7.4.1 Operation as output pin

The PCLBUZn pin is output as the following procedure.
<1> Set 0 in the bit of the port mode register (PMxx) and port register (Pxx) which correspond to the port which has a
pin used as the PCLBUZ0 pin.
<2> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2) of the clock output select register (CKSn) of the
PCLBUZn pin (output in disabled status).
<3> Set bit 7 (PCLOEn) of the CKSn register to 1 to enable clock/buzzer output.
Remarks 1. The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOEn bit) is switched. At this time, pulses with a narrow width are not output.
Figure 7-3 shows enabling or stopping output using the PCLOEn bit and the timing of outputting the clock.
2. n = 0, 1
PCLOEn
Clock output
Narrow pulses are not recognized

7.5 Cautions of Clock Output/Buzzer Output Controller

When the main system clock is selected for the PCLBUZn output (CSEL = 0), if STOP mode is entered within 1.5 clock
cycles output from the PCLBUZn pin after the output is disabled (PCLOEn = 0), the PCLBUZn output width becomes
shorter.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Figure 7-3. Timing of Outputting Clock from PCLBUZn Pin
1 clock elapsed
232