Configuration Of Serial Array Unit - Renesas RL78/G1P Hardware User Manual

RL78/G1P

11.2 Configuration of Serial Array Unit

The serial array unit includes the following hardware.
Item
Shift register
Buffer register
Serial clock I/O
Serial data input
Serial data output
Slave select input
Control registers
Note The lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending on
the communication mode.
 CSIp communication ... SIOp (CSIp data register)
 UARTq reception ... RXDq (UARTq receive data register)
 UARTq transmission ... TXDq (UARTq transmit data register)
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1), p: CSI number (p = 00), q: UART number (q = 0)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 11-1. Configuration of Serial Array Unit
9 bits
Lower 9 bits of serial data register mn (SDRmn)
SCK00 pin (for 3-wire serial I/O)
SI00 pin (for 3-wire serial I/O), R
SO00 pin (for 3-wire serial I/O), T
SSI00 pin (for slave select input function)
<Registers of unit setting block>
 Peripheral enable register 0 (PER0)
 Serial clock select register m (SPSm)
 Serial channel enable status register m (SEm)
 Serial channel start register m (SSm)
 Serial channel stop register m (STm)
 Serial output enable register m (SOEm)
 Serial output register m (SOm)
 Serial output level register m (SOLm)
 Serial standby control register m (SSCm)
 Input switch control register (ISC)
 Noise filter enable register 0 (NFEN0)
<Registers of each channel>
 Serial data register mn (SDRmn)
 Serial mode register mn (SMRmn)
 Serial communication operation setting register mn (SCRmn)
 Serial status register mn (SSRmn)
 Serial flag clear trigger register mn (SIRmn)
 Port mode register 3 (PM3)
 Port register 3 (P3)
CHAPTER 11 SERIAL ARRAY UNIT
Configuration
Note
D0 pin (for UART)
X
D0 pin (for UART), output controller
X
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