Renesas RL78/G1P Hardware User Manual page 14

16-bit single-chip microcontroller
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11.6.2 Slave reception ............................................................................................................................. 412
11.6.3 Slave transmission/reception ........................................................................................................ 419
11.6.4 Calculating transfer clock frequency ............................................................................................. 429
11.6.5 Procedure for processing errors that occurred during slave select input function
communication ............................................................................................................................. 431
11.7 Operation of UART (UART0) Communication ....................................................................... 432
11.7.1 UART transmission ...................................................................................................................... 434
11.7.2 UART reception ............................................................................................................................ 444
11.7.3 SNOOZE mode function ............................................................................................................... 451
11.7.4 Calculating baud rate ................................................................................................................... 459
11.7.5 Procedure for processing errors that occurred during UART (UART0) communication ............... 463
CHAPTER 12 SERIAL INTERFACE IICA ........................................................................................... 464
12.1 Functions of Serial Interface IICA ........................................................................................... 464
12.2 Configuration of Serial Interface IICA .................................................................................... 467
12.3 Registers Controlling Serial Interface IICA ............................................................................ 470
12.3.1 Peripheral enable register 0 (PER0) ............................................................................................. 470
12.3.2 IICA control register n0 (IICCTLn0) .............................................................................................. 471
12.3.3 IICA status register n (IICSn) ........................................................................................................ 476
12.3.4 IICA flag register n (IICFn) ............................................................................................................ 478
12.3.5 IICA control register n1 (IICCTLn1) .............................................................................................. 480
12.3.6 IICA low-level width setting register n (IICWLn) ........................................................................... 482
12.3.7 IICA high-level width setting register n (IICWHn) ......................................................................... 482
12.3.8 Port mode register 6 (PM6) .......................................................................................................... 483
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12.4 I
C Bus Mode Functions .......................................................................................................... 484
12.4.1 Pin configuration ........................................................................................................................... 484
12.4.2 Setting transfer clock by using IICWLn and IICWHn registers ...................................................... 485
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12.5 I
C Bus Definitions and Control Methods .............................................................................. 487
12.5.1 Start conditions ............................................................................................................................. 487
12.5.2 Addresses .................................................................................................................................... 488
12.5.3 Transfer direction specification ..................................................................................................... 488
12.5.4 Acknowledge (ACK) ..................................................................................................................... 489
12.5.5 Stop condition ............................................................................................................................... 490
12.5.6 Wait .............................................................................................................................................. 491
12.5.7 Canceling wait .............................................................................................................................. 493
12.5.8 Interrupt request (INTIICAn) generation timing and wait control ................................................... 494
12.5.9 Address match detection method ................................................................................................. 495
12.5.10 Error detection ............................................................................................................................ 495
12.5.11 Extension code ........................................................................................................................... 495
12.5.12 Arbitration ................................................................................................................................... 496
12.5.13 Wakeup function ......................................................................................................................... 498
Index-8

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