Renesas RL78/G1P Hardware User Manual page 201

RL78/G1P
Figure 6-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2)
(a) Timer mode register mn (TMRmn)
15 14
TMRmn
CKSmn1 CKSmn0
1/0 1/0
Operation clock (f
(b) Timer output register m (TOm)
Bit n
TOm
TOmn
1/0
(c) Timer output enable register m (TOEm)
Bit n
TOEm
TOEmn
1/0
Note TMRm2:
TMRm1, TMRm3: SPLITmn bit
TMRm0:
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
13 12 11 10
Note
CCSmn STSmn2 STSmn1
M/S
0 0 0/1 0
Setting of MASTERmn bit (channel 2)
0: Independent channel operation function.
Setting of SPLITmn bit (channels 1, 3)
0: 16-bit timer mode
1: 8-bit timer mode
Count clock selection
0: Selects operation clock (f
) selection
MCK
00B: Selects CKm0 as operation clock of channel n.
10B: Selects CKm1 as operation clock of channel n.
01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
0: Outputs 0 from TOmn.
1: Outputs 1 from TOmn.
0: Stops the TOmn output operation by counting operation.
1: Enables the TOmn output operation by counting operation.
MASTERmn bit
Fixed to 0
9 8 7 6 5
STSmn0 CISmn1 CISmn0
0 0 0 0 0
Operation mode of channel n
000B: Interval timer
Selection of TImn pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
).
MCK
CHAPTER 6 TIMER ARRAY UNIT
4 3 2 1
MDmn3 MDmn2 MDmn1
0 0 0 0
Setting of operation when counting is started
0: Neither generates INTTMmn nor inverts
timer output when counting is started.
1: Generates INTTMmn and inverts timer
output when counting is started.
0
MDmn0
1/0
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