Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode)

<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel
specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the
hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that
specified by scan 0.
<3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
conversion of the channel following the specified channel automatically starts.
<4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 9-27. Example of Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
<1> ADCE is set to 1.
ADCE
<2> A hardware trigger
is generated.
Hardware
trigger
The trigger is not
Trigger
acknowledged. standby status
ADCS
ADS
ANI0 to ANI3
A/D
Data 2
Data 1
conversion Stop status
(ANI0) (ANI1)
status
A/D power supply
stabilization wait
Data 1
ADCR,
(ANI0)
ADCRH
INTAD
The interrupt is generated four times.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Operation Timing
A hardware trigger is
<4>
generated during A/D
conversion operation.
A/D conversion
<3>
Conversion is
ends and the next
interrupted and restarts.
conversion starts.
Data 3 Data 4 Data 5 Data 7 Data 8 Data 9
Data 6
(ANI2) (ANI3) (ANI0) (ANI1) (ANI0) (ANI1) (ANI2)
Data 4
Data 2 Data 3 Data 5 Data 7 Data 8
(ANI1) (ANI2) (ANI3) (ANI1)
(ANI0) (ANI0)
The interrupt is generated four times.
After A/D conversion of the four channels ends, the A/D
conversion operation.
ADS is rewritten during
<5>
A/D conversion operation.
ANI4 to ANI7
<3> <3>
Conversion is
interrupted and restarts.
Data 10 Data Data 13 Data 14 Data 15
Data 11 Data 16
12
(ANI3) (ANI0) (ANI4) (ANI5) (ANI6) (ANI7)
(ANI1)
Data 9 Data 14 Data 15
Data 10 Data 11 Data 13
(ANI2) (ANI3) (ANI0) (ANI4) (ANI5) (ANI6)
The interrupt is generated four times.
CHAPTER 9 A/D CONVERTER
ADCS is overwritten ADCS is cleared
<6>
with 1 during A/D to 0 during A/D
conversion operation.
Conversion is <3>
interrupted and restarts.
Data 17 Data 18 Data Data 20 Data 21 Data 23
Data 22
19
(ANI4) (ANI5) (ANI4) (ANI5) (ANI6) (ANI7)
(ANI6)
Data 17 Data 20 Data 22
Data 16 Data 18 Data 21
(ANI7) (ANI4) (ANI5) (ANI4) (ANI5) (ANI6)
The interrupt is generated four times.
Trigger
The trigger is not
standby
acknowledged.
status
<7>
Conversion is
interrupted.
Data 24
Stop status
(ANI4)
Data 23
(ANI7)
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