Renesas RL78/G1P Hardware User Manual page 60

16-bit single-chip microcontroller
Hide thumbs Also See for RL78/G1P:
Table of Contents

Advertisement

RL78/G1P
Address
Special Function Register (SFR) Name
FFF64H
Timer data register 02
FFF65H
FFF66H
Timer data register 03
FFF67H
FFFA0H
Clock operation mode control register
FFFA1H
Clock operation status control register
FFFA2H
Oscillation stabilization time counter status
register
FFFA3H
Oscillation stabilization time select register
FFFA4H
System clock control register
FFFA5H
Clock output select register 0
FFFA6H
Clock output select register 1
FFFA8H
Reset control flag register
FFFA9H
Voltage detection register
FFFAAH
Voltage detection level register
FFFABH
Watchdog timer enable register
FFFACH
CRC input register
FFFB0H
DMA SFR address register 0
FFFB1H
DMA SFR address register 1
FFFB2H
DMA RAM address register 0L
FFFB3H
DMA RAM address register 0H
FFFB4H
DMA RAM address register 1L
FFFB5H
DMA RAM address register 1H
FFFB6H
DMA byte count register 0L
FFFB7H
DMA byte count register 0H
FFFB8H
DMA byte count register 1L
FFFB9H
DMA byte count register 1H
FFFBAH
DMA mode control register 0
FFFBBH
DMA mode control register 1
FFFBCH
DMA operation control register 0
FFFBDH
DMA operation control register 1
Notes 1. The reset value of the RESF register varies depending on the reset source.
2. The reset value of the LVIM register varies depending on the reset source.
3. The reset value of the LVIS register varies depending on the reset source and the setting of the option byte.
4. The reset value of the WDTE register is determined by the setting of the option byte.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 3-5. Special Function Register (SFR) (2/3)
Symbol
TDR02
TDR03L TDR03
TDR03H
CMC
CSC
OSTC
OSTS
CKC
CKS0
CKS1
RESF
LVIM
LVIS
WDTE
CRCIN
DSA0
DSA1
DRA0L
DRA0H
DRA1L
DRA1H
DBC0L
DBC0H
DBC1L
DBC1H
DMC0
DMC1
DRC0
DRC1
CHAPTER 3 CPU ARCHITECTURE
Manipulable Bit Range
R/W
1-bit
8-bit
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
DRA0
R/W
R/W
DRA1
R/W
R/W
DBC0
R/W
R/W
DBC1
R/W
R/W
R/W
R/W
R/W
R/W
After Reset
16-bit
0000H
00H
00H
00H
C0H
00H
07H
00H
00H
00H
Undefined
Note 1
Note 2
00H
00H/01H/81H
Note 3
1AH/9AH
Note 4
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
41

Advertisement

Table of Contents
loading

Table of Contents