Renesas RL78/G1P Hardware User Manual page 200

RL78/G1P
Figure 6-41. Block Diagram of Operation as Interval Timer/Square Wave Output
CKm1
Note
Operation clock
CKm0
TSmn
Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Figure 6-42. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MDmn0 = 1)
TCRmn
TDRmn
INTTMmn
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 3)
2. TSmn:
TEmn:
TCRmn:
TDRmn:
TOmn:
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
TSmn
TEmn
0000H
a
TOmn
a+1
Bit n of timer channel start register m (TSm)
Bit n of timer channel enable status register m (TEm)
Timer count register mn (TCRmn)
Timer data register mn (TDRmn)
TOmn pin output signal
Timer counter
register mn (TCRmn)
Timer data
register mn(TDRmn)
a+1 a+1 b+1
CHAPTER 6 TIMER ARRAY UNIT
Output
controller
Interrupt
Interrupt signal
controller
(INTTMmn)
b
b+1 b+1
TOmn pin
181