Register Indirect Addressing - Renesas RL78/G1P Hardware User Manual

RL78/G1P

3.4.6 Register indirect addressing

[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair specified
with the instruction word as an operand address.
[Operand format]
Identifier

[DE], [HL] (only the space from F0000H to FFFFFH is specifiable)

ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
[DE], [HL]
<1>
Instruction code
OP-code
Either pair of registers <1> specifies the target
location as an address in the 64 KB area from
F0000H to FFFFFH.
ES: [DE],
<1> <2>
Instruction code
OP-code
The ES register <1> specifies a 64 KB area within the
overall 1 MB space as the four higher-order bits, X, of
the address range.
Either pair of registers <2> and the ES register <1> specify
the target location in the area from X0000H to XFFFFH.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 3-21. Example of [DE], [HL]
<1>
<1>
rp(HL/DE)
Figure 3-22. Example of ES:[DE], ES:[HL]
ES: [HL]
<1> <2>
<2>
rp(HL/DE)
<1>
ES
CHAPTER 3 CPU ARCHITECTURE
Description
<1>
Specifies the
address in memory
<2>
Specifies the
address in memory
X0000H
Specifies a
<1>
64 KB area
FFFFFH
Target memory
F0000H
Memory
FFFFFH
Area from
Target memory
X0000H to
XFFFFH
00000H
Memory
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