Setting Window Open Period Of Watchdog Timer - Renesas RL78/G1P Hardware User Manual

16-bit single-chip microcontroller
Hide thumbs Also See for RL78/G1P:
Table of Contents

Advertisement

RL78/G1P

8.4.3 Setting window open period of watchdog timer

Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
(000C0H). The outline of the window is as follows.
 If "ACH" is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer
is cleared and starts counting again.
 Even if "ACH" is written to the WDTE register during the window close period, an abnormality is detected and an
internal reset signal is generated.
Example: If the window open period is 50%
Counting
Caution When data is written to the WDTE register for the first time after reset release, the watchdog timer is
cleared in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
starts
Window close period (50%)
Internal reset signal is generated
if "ACH" is written to WDTE.
CHAPTER 8 WATCHDOG TIMER
Overflow
Window open period (50%)
Counting starts again when
"ACH" is written to WDTE.
time
238

Advertisement

Table of Contents
loading

Table of Contents