Renesas RL78/G1P Hardware User Manual page 734

RL78/G1P
Instruction Mnemonic
Group
Bit XOR1 CY, A.bit
manipulate
CY, PSW.bit
CY, saddr.bit
CY, sfr.bit
CY, [HL].bit
CY, ES:[HL].bit
SET1 A.bit
PSW.bit
!addr16.bit
ES:!addr16.bit
saddr.bit
sfr.bit
[HL].bit
ES:[HL].bit
CLR1 A.bit
PSW.bit
!addr16.bit
ES:!addr16.bit
saddr.bit
sfr.bit
[HL].bit
ES:[HL].bit
SET1 CY
CLR1 CY
NOT1 CY
Notes 1. Number of CPU clocks (f
when no data is accessed
2. Number of CPU clocks (f
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 26-5. Operation List (15/18)
Operands Bytes
Note 1 Note 2
2
3
3
3
2
3
2
3
4
5
3
3
2
3
2
3
4
5
3
3
2
3
2
2
2
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the program memory area is accessed.
CLK
Clocks
 CY  CY  A.bit
1
 CY  CY  PSW.bit
1
 CY  CY  (saddr).bit
1
 CY  CY  sfr.bit
1
CY  CY  (HL).bit
1 4
CY  CY  (ES, HL).bit
2 5
 A.bit  1
1
 PSW.bit  1
4
 (addr16).bit  1
2
 (ES, addr16).bit  1
3
 (saddr).bit  1
2
 sfr.bit  1
2
 (HL).bit  1
2
 (ES, HL).bit  1
3
 A.bit  0
1
 PSW.bit  0
4
 (addr16).bit  0
2
 (ES, addr16).bit  0
3
 (saddr.bit)  0
2
 sfr.bit  0
2
 (HL).bit  0
2
 (ES, HL).bit  0
3
 CY  1
1
 CY  0
1
 CY  CY
1
CHAPTER 26 INSTRUCTION SET
Operation Flag
Z AC CY
×
×
×
×
×
×
× × ×
× × ×
1
0
×
715