Serial Channel Stop Register M (Stm) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

11.3.9 Serial channel stop register m (STm)

The STm register is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m
(SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared immediately when SEmn =
0.
The STm register can set written by a 16-bit memory manipulation instruction.
The lower 8 bits of the STm register can be set with a 1-bit or 8-bit memory manipulation instruction with STmL.
Reset signal generation clears the STm register to 0000H.
Address: F0124H, F0125H (ST0)
Symbol 15 14
ST0 0 0
STm
n
0 No trigger operation
Clears the SEmn bit to 0 and stops the communication operation
1
Note Holding status value of the control register and shift register, the SCKmn and SOmn pins, and FEFmn, PEFmn,
OVFmn flags.
Caution Be sure to clear bits 15 to 2 to "0".
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 1)
2. When the STm register is read, 0000H is always read.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 11-11. Format of Serial Channel Stop Register m (STm)
After reset: 0000H W
13 12 11 10
0 0 0 0
Operation stop trigger of channel n
CHAPTER 11 SERIAL ARRAY UNIT
9 8 7 6
0 0 0 0
Note
5 4 3 2
0 0 0 0 ST01 ST00
.
1 0
327