Renesas RL78/G1P Hardware User Manual page 377

RL78/G1P
Figure 11-39. Flowchart of Master Reception (in Continuous Reception Mode)
Write MDmn0 bit to 1
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 11-38 Timing Chart of Master Reception
(in Continuous Reception Mode).
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Starting CSI communication
SAU default setting
<1>
Setting receive data
Enables interrupt
Writing dummy data to
<2>
SIOp (= SDRmn [7:0])
Wait for receive completes
<3><6>
Buffer empty/transfer end interrupt
BFFmn = 1?
Yes
<4>
Reading receive data to SIOp
(= SDRmn [7:0])
<7>
Subtract -1 from number of
transmit data
= 0
Number of communication
data?
<5>
= 1
Clear MDmn0 bit to 0
RETI
No
Number of communication
data = 0 ?
Yes
Yes
Communication continued?
No
Disable interrupt (MASK)
<8> Write STmn bit to 1
End of communication
CHAPTER 11 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 11-33.
(Select buffer empty interrupt)
Setting storage area of the receive data, number of
communication data
(Storage area, Reception data pointer, Number of
communication data and Communication end flag are
optionally set on the internal RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask
(XXMK) and set interrupt enable (EI)
Writing to SIOp makes SCKp
signals out (communication starts)
When interrupt is generated, it moves to
interrupt processing routine
No
Read receive data, if any, then write them to
storage area, and update receive data pointer
(also subtract -1 from number of transmit data)
≥ 2
<2>
Writing dummy data to
SIOp (= SDRmn [7:0])
When number of communication data
becomes 0, receive completes
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