Renesas RL78/G1P Hardware User Manual page 187

RL78/G1P
(5) Operation of capture & one-count mode (high-level width measurement)
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm).
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of 0000H is loaded to the TCRmn register and count starts.
<5> On detection of the falling edge of the TImn input, the value of the TCRmn register is captured to timer data
register mn (TDRmn) and INTTMmn is generated.
Figure 6-29. Operation Timing (In Capture & One-count Mode : High-level Width Measurement)
f
MCK
(f )
TCLK
TSmn (write)
TEmn
TImn input
Rising edge
Falling edge
Start trigger
detection signal
TCRmn
TDRmn
INTTMmn
Remark The above figure shows the timing when the noise filter is not in use. By making the noise filter on-state,
the edge detection becomes 2 f
TImn input. The error per one period occurs be the asynchronous between the period of the TImn input
and that of the count clock (f
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
<1>
<3>
Edge detection
<2>
Initial value
cycles (it sums up to 3 to 4 cycles) later than the normal cycle of
MCK
).
MCK
CHAPTER 6 TIMER ARRAY UNIT
Edge detection
<4>
0000
0000
<5>
m
m+1
m1
m
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