A/D Converter Conversion Operations - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.4 A/D Converter Conversion Operations

The A/D converter conversion operations are described below.
<1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
<3> Bit 11 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2)
AV by the tap selector.
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<4> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than (1/2) AV
to 1. If the analog input is smaller than (1/2) AV
<5> Next, bit 10 of the SAR register is automatically set to 1, and the operation proceeds to the next comparison. The
series resistor string voltage tap is selected according to the preset value of bit 11, as described below.
 Bit 11 = 1: (3/4) AV
 Bit 11 = 0: (1/4) AV
The voltage tap and sampled voltage are compared and bit 10 of the SAR register is manipulated as follows.
 Sampled voltage  Voltage tap: Bit 10 = 1
 Sampled voltage < Voltage tap: Bit 10 = 0
<6> Comparison is continued in this way up to bit 0 of the SAR register.
<7> Upon completion of the comparison of 12 bits, an effective digital result value remains in the SAR register, and
the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated
<8> Repeat steps <1> to <7>, until the ADCS bit is cleared to 0
To stop the A/D converter, clear the ADCS bit to 0.
If the A/D conversion result is outside the A/D conversion result range specified by the ADRCK bit and the
Notes 1.
ADUL and ADLL registers (see Figure 9-8), the A/D conversion result interrupt request signal is not
generated and no A/D conversion results are stored in the ADCR and ADCRH registers.
While in the sequential conversion mode, the ADCS flag is not automatically cleared to 0. This flag is not
2.
automatically cleared to 0 while in the one-shot conversion mode of the hardware trigger no-wait mode,
either. Instead, 1 is retained.
Remarks 1. Two types of the A/D conversion result registers are available.
 ADCR register (16 bits): Store 12-bit A/D conversion value
 ADCRH register (8 bits): Store 8-bit A/D conversion value
2. AV : The + side reference voltage of the A/D converter. This can be selected from AV
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R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
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internal reference voltage (1.45 V), and V
, the MSB bit of the SAR register remains set
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, the MSB bit is reset to 0.
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.
Note 2
.
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CHAPTER 9 A/D CONVERTER
Note 1
.
Note 1
.
, the
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