Renesas RL78/G1P Hardware User Manual page 682

RL78/G1P
22.2 Format of User Option Byte
Address: 000C0H
7
WDTINIT
WDTINIT
0
1
WINDOW1
0
0
1
1
WDTON
0
1
WDCS2
0
0
0
0
1
Other than above
WDSTBYON
0
1
Note The window open period is 100% when WDSTBYON = 0, regardless the value of the WINDOW1 and
WINDOW0 bits.
Caution The watchdog timer continues its operation even during self-programming or data flash rewrite.
During processing, the interrupt acknowledge time is delayed. Set the overflow time and window
size taking this delay into consideration.
Remark f : Low-speed on-chip oscillator clock frequency
IL
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 22-1. Format of User Option Byte (000C0H)
6 5
WINDOW1 WINDOW0
Interval interrupt is not used.
Interval interrupt is generated when 75% of the overflow time + 1/2f
WINDOW0
0 Setting prohibited
1 50%
0 75%
1 100%
Operation control of watchdog timer counter
Counter operation disabled (counting stopped after reset)
Counter operation enabled (counting started after reset)
WDCS1 WDCS0
0 0
0 1
1 0
1 1
0 0
Operation control of watchdog timer counter (HALT/STOP mode)
Counter operation stopped in HALT/STOP mode
Counter operation enabled in HALT/STOP mode
4 3
WDTON WDCS2
Use of interval interrupt of watchdog timer
Watchdog timer window open period
Watchdog timer overflow time
(f = 17.25 kHz (MAX.))
IL
6
2 /f (3.71 ms)
IL
7
2 /f (7.42 ms)
IL
8
2 /f (14.84 ms)
IL
9
2 /f (29.68 ms)
IL
11
2 /f (118.72 ms)
IL
Setting prohibited
Note
CHAPTER 22 OPTION BYTE
2 1
WDCS1 WDCS0 WDSTBYON
is reached.
IL
Note
0
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