Peripheral Enable Registers 0, 1 (Per0, Per1) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

5.3.6 Peripheral enable registers 0, 1 (PER0, PER1)

These registers are used to enable or disable supply of the clock signal to peripheral hardware. Clock supply to a
hardware that is not in use is stopped in order to reduce power consumption and noise.
To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each
function before specifying the initial settings of the peripheral functions.
 Serial interface IICA1
 A/D converter
 D/A converter
 Serial interface IICA0
 Serial array unit 0
 Timer array unit 0
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Address: F00F0H
Symbol 7
PER0 0
IICA1EN
0
1
ADCEN
0
1
IICA0EN
0
1
Caution Be sure to clear bits 1, 3 and 7 to "0".
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (1/2)
After reset: 00H R/W
<6> <5>
IICA1EN ADCEN
Control of serial interface IICA1 input clock supply
Stops input clock supply.
 SFR used by the serial interface IICA1 cannot be written.
 The serial interface IICA1 is in the reset status.
Enables input clock supply.
 SFR used by the serial interface IICA1 can be read and written.
Stops input clock supply.
 SFR used by the A/D converter cannot be written.
 The A/D converter is in the reset status.
Enables input clock supply.
 SFR used by the A/D converter can be read and written.
Control of serial interface IICA0 input clock supply
Stops input clock supply.
 SFR used by the serial interface IICA0 cannot be written.
 The serial interface IICA0 is in the reset status.
Enables input clock supply.
 SFR used by the serial interface IICA0 can be read and written.
<4> 3
IICA0EN 0
Control of A/D converter input clock supply
CHAPTER 5 CLOCK GENERATOR
<2> 1
SAU0EN 0
<0>
TAU0EN
107