Setting Watchdog Timer Interval Interrupt - Renesas RL78/G1P Hardware User Manual

RL78/G1P

8.4.4 Setting watchdog timer interval interrupt

Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be
generated when 75% of the overflow time + 1/2f
WDTINT
0 Interval interrupt is used.
1 Interval interrupt is generated when 75% of the overflow time + 1/2f
Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an
overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP
mode release by an interval interrupt.
Remark The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the
watchdog timer enable register (WDTE)). If ACH is not written to the WDTE register before the overflow time,
an internal reset signal is generated.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
is reached.
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Table 8-5. Setting of Watchdog Timer Interval Interrupt
Use of Watchdog Timer Interval Interrupt
CHAPTER 8 WATCHDOG TIMER
is reached.
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