Renesas RL78/G1P Hardware User Manual page 753

RL78/G1P
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(T = -40 to +85C, 2.7 V ≤ V
A
Parameter
SCKp cycle time
SCKp high-/low-level width
Note 1
SIp setup time (to SCKp↑)
SIp hold time (from SCKp↑)
Delay time from SCKp↓ to SOp output
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp↓" and
the SIp hold time becomes "from SCKp↓" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
"from SCKp↑" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. C is the load capacitance of the SCKp and SOp output lines.
Remarks 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0)
2. f : Serial array unit operation clock frequency
MCK
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
≤ 3.6 V, V = 0 V)
DD SS
Symbol
t
KCY1
t , t
KH1 KL1
t
SIK1
Note 1 t
KSI1
Note 2
t C = 20 pF
KSO1
CHAPTER 27 ELECTRICAL SPECIFICATIONS
Conditions HS (high-speed main) Mode LS (low-speed main) Mode Unit
MIN.
83.3
t /2 - 10
KCY1
33
10
Note 3
MAX. MIN. MAX.
250
t /2 - 50
KCY1
110
10
10
ns
ns
ns
ns
ns
10
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