Renesas RL78/G1P Hardware User Manual page 525
16-bit single-chip microcontroller
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RL78/G1P
12.5.16 Communication operations
The following shows three operation procedures with the flowchart.
(1) Master operation in single master system
The flowchart when using the RL78/G1P as the master in a single master system is shown below.
This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings
at startup.
If communication with the slave is required, prepare the communication and then execute
communication processing.
(2) Master operation in multimaster system
2
In the I
C bus multimaster system, whether the bus is released or used cannot be judged by the I
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the RL78/G1P takes part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the RL78/G1P looses in arbitration and is specified as the slave is omitted here, and only the
processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then,
wait for the communication request as the master or wait for the specification as the slave.
communication is performed in the communication processing, and it supports the transmission/reception with the
slave and the arbitration with other masters.
(3) Slave operation
An example of when the RL78/G1P is used as the I
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the
INTIICAn interrupt occurrence (communication waiting). When an INTIICAn interrupt occurs, the communication
status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 12 SERIAL INTERFACE IICA
2
C bus slave is shown below.
2
C bus
The actual
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