Renesas RL78/G1P Hardware User Manual page 664

RL78/G1P
20.3.1 Flash memory CRC control register (CRC0CTL)
This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range.
The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 20-1. Format of Flash Memory CRC Control Register (CRC0CTL)
Address: F02F0H After reset: 00H
Symbol <7>
CRC0CTL CRC0EN
CRC0EN
0
1
FEA5
0
Remark Input the expected CRC operation result value to be used for comparison in the lowest 4 bytes of the flash
memory. Note that the operation range will thereby be reduced by 4 bytes.
20.3.2 Flash memory CRC operation result register (PGCRCL)
This register is used to store the high-speed CRC operation results.
The PGCRCL register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 20-2. Format of Flash Memory CRC Operation Result Register (PGCRCL)
Address: F02F2H After reset: 0000H
Symbol 15
PGCRCL PGCRC15
7
PGCRC7
PGCRC15 to PGCRC0
0000H to FFFFH
Caution The PGCRCL register can only be written if CRC0EN (bit 7 of the CRC0CTL register) = 1.
Figure 20-3 shows the flowchart of flash memory CRC operation function (high-speed CRC).
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
R/W
6 5
0 FEA5
Stop the operation.
Start the operation according to HALT instruction execution.
FEA4 FEA3 FEA2
0 0 0
Other than above
R/W
14 13
PGCRC14 PGCRC13
6 5
PGCRC6 PGCRC5
Store the high-speed CRC operation results.
CHAPTER 20 SAFETY FUNCTIONS
4 3
FEA4 FEA3
Control of CRC ALU operation
FEA1 FEA0
0 0 0000H to 3FFBH (16 K to 4 bytes)
Setting prohibited
12 11
PGCRC12 PGCRC11
4 3
PGCRC4 PGCRC3
High-speed CRC operation results
2 1
FEA2 FEA1
High-speed CRC operation range
10 9
PGCRC10 PGCRC9
2 1
PGCRC2 PGCRC1
0
FEA0
8
PGCRC8
0
PGCRC0
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