Renesas RL78/G1P Hardware User Manual page 185

RL78/G1P
(3) Operation of capture mode (input pulse interval measurement)
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Timer count register mn (TCRmn) holds the initial value until count clock generation.
<3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is loaded
to the TCRmn register and counting starts in the capture mode. (When the MDmn0 bit is set to 1, INTTMmn is
generated by the start trigger.)
<4> On detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer data
register mn (TDRmn) and INTTMmn is generated. However, this capture value is nomeaning. The TCRmn
register keeps on counting from 0000H.
<5> On next detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer
data register mn (TDRmn) and INTTMmn is generated.
Figure 6-27. Operation Timing (In Capture Mode: Input Pulse Interval Measurement)
f
MCK
(f )
TCLK
TS0n (write)
TE0n
TI0n input
Rising edge
Start trigger
detection signal
TCR0n
TDR0n
INTTM0n
Note If a clock has been input to TImn (the trigger exists) when capturing starts, counting starts when a trigger is
detected, even if no edge is detected. Therefore, the first captured value (<4>) does not determine a pulse
interval (in the above figure, 0001 just indicates two clock cycles but does not determine the pulse interval)
and so the user can ignore it.
Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MDmn0 = 1.
Remark The above figure shows the timing when the noise filter is not in use. By making the noise filter on-state,
the edge detection becomes 2 f
TImn input. The error per one period occurs be the asynchronous between the period of the TImn input
and that of the count clock (f
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
<1>
Note
<3>
Edge detection
<3>
<2>
0000
Initial value
When MDmn0 = 1
cycles (it sums up to 3 to 4 cycles) later than the normal cycle of
MCK
).
MCK
<4>
0001 0000
0001
Note
CHAPTER 6 TIMER ARRAY UNIT
Edge detection
<5>
m
m1
0000
m
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