Renesas RL78/G1P Hardware User Manual page 521

16-bit single-chip microcontroller
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RL78/G1P
Figure 12-25 shows the communication reservation timing.
Program processing
Hardware processing
SCLAn
1
2
SDAAn
Remark
IICAn:
STTn:
STDn: Bit 1 of IICA status register n (IICSn)
SPDn: Bit 0 of IICA status register n (IICSn)
Communication reservations are accepted via the timing shown in Figure 12-26. After bit 1 (STDn) of the IICA
status register n (IICSn) is set to 1, a communication reservation can be made by setting bit 1 (STTn) of IICA
control register n0 (IICCTLn0) to 1 before a stop condition is detected.
SCLAn
SDAAn
STDn
SPDn
Standby mode (Communication can be reserved by setting STTn to 1 during this period.)
Figure 12-27 shows the communication reservation protocol.
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-25. Communication Reservation Timing
STTn = 1
Communi-
cation
reservation
3
4
5
6
7
IICA shift register n
Bit 1 of IICA control register n0 (IICCTLn0)
Figure 12-26. Timing for Accepting Communication Reservations
CHAPTER 12 SERIAL INTERFACE IICA
Write to
IICAn
Set SPDn
and
INTIICAn
8
9
Generate by master device with bus mastership
Set
STDn
1
2
3
4
5
6
502

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