Renesas RL78/G1P Hardware User Manual page 527

RL78/G1P
(2) Master operation in multi-master system
START
Setting port
IICWLn, IICWHn ← XXH
SVAn ← XXH
IICFn ← 0XH
Setting STCENn and IICRSVn
Setting IICCTLn1
IICCTLn0 ← 0XX111XXB
ACKEn = WTIMn = SPIEn = 1
IICCTLn0 ← 1XX111XXB
IICEn = 1
Setting port
Checking bus status
INTIICAn
No
interrupt occurs?
SPDn = 1?
1
Master operation
starts?
Yes
SPIEn = 1
IICRSVn = 0?
A
Enables reserving
communication.
Note Confirm that the bus is released (CLDn bit = 1, DADn bit = 1) for a specific period (for example, for a period of
one frame). If the SDAAn pin is constantly at low level, decide whether to release the I
SDAAn pins = high level) in conformance with the specifications of the product that is communicating.
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-29. Master Operation in Multi-Master System (1/3)
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0
Selects a transfer clock.
Sets a local address.
Sets a start condition.
Set the port from input mode to output mode and enable the output of the
(see 12.3.8 Port mode register 6 (PM6)).
Releases the bus for a specific period.
Note
Bus status is
STCENn = 1?
being checked.
Yes
No
Yes
Slave operation
• Waiting to be specified as a slave by other master
• Waiting for a communication start request (depends on user program)
No
(No communication start request)
(Communication start request)
No
Yes
B
Disables reserving
communication.
CHAPTER 12 SERIAL INTERFACE IICA
(see 12.3.8 Port mode register 6 (PM6)).
No
Yes
interrupt occurs?
SPDn = 1?
SPIEn = 0
INTIICAn
No
interrupt occurs?
Waits for a communication request.
Yes
Slave operation
2
I C bus
Prepares for starting
communication
SPTn = 1
(generates a stop condition).
INTIICAn
No
Waits for detection
of the stop condition.
Yes
No
Yes
Slave operation
2
C bus (SCLAn and
508