Renesas RL78/G1P Hardware User Manual page 11

6.9.1 Operation as one-shot pulse output function .................................................................................. 204
6.9.2 Operation as PWM function ............................................................................................................ 211
6.9.3 Operation as multiple PWM output function ................................................................................... 218
6.10 Cautions When Using Timer Array Unit ................................................................................. 226
6.10.1 Cautions when using timer output ................................................................................................ 226
CHAPTER 7 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ................................................. 227
7.1 Functions of Clock Output/Buzzer Output Controller ............................................................ 227
7.2 Configuration of Clock Output/Buzzer Output Controller ...................................................... 229
7.3 Registers Controlling Clock Output/Buzzer Output Controller ............................................. 229
7.3.1 Clock output select registers n (CKSn) ........................................................................................... 229
7.3.2 Registers controlling port functions of pins to be used for clock or buzzer output .......................... 231
7.4 Operations of Clock Output/Buzzer Output Controller .......................................................... 232
7.4.1 Operation as output pin .................................................................................................................. 232
7.5 Cautions of Clock Output/Buzzer Output Controller .............................................................. 232
CHAPTER 8 WATCHDOG TIMER ....................................................................................................... 233
8.1 Functions of Watchdog Timer ................................................................................................... 233
8.2 Configuration of Watchdog Timer ............................................................................................ 234
8.3 Register Controlling Watchdog Timer ...................................................................................... 235
8.3.1 Watchdog timer enable register (WDTE) ........................................................................................ 235
8.4 Operation of Watchdog Timer ................................................................................................... 236
8.4.1 Controlling operation of watchdog timer ......................................................................................... 236
8.4.2 Setting overflow time of watchdog timer ......................................................................................... 237
8.4.3 Setting window open period of watchdog timer .............................................................................. 238
8.4.4 Setting watchdog timer interval interrupt ........................................................................................ 240
CHAPTER 9 A/D CONVERTER ........................................................................................................... 241
9.1 Function of A/D Converter ......................................................................................................... 241
9.2 Configuration of A/D Converter ................................................................................................ 244
9.3 Registers Controlling A/D Converter ........................................................................................ 246
9.3.1 Peripheral enable register 0 (PER0) ............................................................................................... 247
9.3.2 A/D converter mode register 0 (ADM0) .......................................................................................... 248
9.3.3 A/D converter mode register 1 (ADM1) .......................................................................................... 257
9.3.4 A/D converter mode register 2 (ADM2) .......................................................................................... 258
9.3.5 12-bit A/D conversion result register (ADCR) ................................................................................. 261
9.3.6 8-bit A/D conversion result register (ADCRH) ................................................................................ 262
9.3.7 Analog input channel specification register (ADS) .......................................................................... 263
9.3.8 Conversion result comparison upper limit setting register (ADUL) ................................................. 265
9.3.9 Conversion result comparison lower limit setting register (ADLL) .................................................. 265
Index-5