Renesas RL78/G1P Hardware User Manual page 528

RL78/G1P
A
STTn = 1
Wait
MSTSn = 1?
C
B
IICBSYn = 0?
D
STTn = 1
Wait
STCFn = 0?
C
Note The wait time is calculated as follows.
(IICWLn setting value + IICWHn setting value + 4)  f
Remarks 1. IICWLn: IICA low-level width setting register n
IICWHn: IICA high-level width setting register n
t :
F
f :
CLK
2. n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-29. Master Operation in Multi-Master System (2/3)
Enables reserving communication.
Prepares for starting communication
(generates a start condition).
Secure wait time
No
Yes
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
Disables reserving communication.
No
Yes
Prepares for starting communication
(generates a start condition).
Note
No
Yes
SDAAn and SCLAn signal falling times
CPU/peripheral hardware clock frequency
CHAPTER 12 SERIAL INTERFACE IICA
Note
by software.
INTIICAn
interrupt occurs?
Yes
No
EXCn = 1 or COIn = 1?
Yes
Slave operation
INTIICAn
interrupt occurs?
Yes
EXCn = 1 or COIn = 1?
Yes
Slave operation
 2 [clocks]
+ t
CLK F
No
Waits for bus release
(communication being reserved).
No
Waits for bus release
No
Detects a stop condition.
D
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