Renesas RL78/G1P Hardware User Manual page 553

RL78/G1P
12.6 Timing Charts
2
When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave
devices as its communication partner.
After outputting the slave address, the master device transmits the TRCn bit (bit 3 of the IICA status register n (IICSn)),
which specifies the data transfer direction, and then starts serial communication with the slave device.
Figures 12-32 and 12-33 show timing charts of the data communication.
The IICA shift register n (IICAn)'s shift operation is synchronized with the falling edge of the serial clock (SCLAn). The
transmit data is transferred to the SO latch and is output (MSB first) via the SDAAn pin.
Data input via the SDAAn pin is captured into IICAn at the rising edge of SCLAn.
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 12 SERIAL INTERFACE IICA
534