Renesas RL78/G1P Hardware User Manual page 571

RL78/G1P
13.2.3 DMA byte count register n (DBCn)
This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the
number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times).
Each time DMA transfer has been executed, this register is automatically decremented. By reading this DBCn register
during DMA transfer, the remaining number of times of transfer can be learned.
The DBCn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 0000H.
Address: FFFB6H, FFFB7H (DBC0), FFFB8H, FFFB9H (DBC1)
15
DBCn 0
(n = 0, 1)
DBCn[9:0]
000H
001H
002H
003H



3FEH
3FFH
Cautions 1. Be sure to clear bits 15 to 10 to "0".
2. If the general-purpose register is specified or the internal RAM space is exceeded as a result of
continuous transfer, the general-purpose register or SFR space are written or read, resulting in
loss of data in these spaces. Be sure to set the number of times of transfer that is within the
internal RAM space.
Remark n: DMA channel number (n = 0, 1)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 13-3. Format of DMA Byte Count Register n (DBCn)
DBC0H: FFFB7H
DBC1H: FFFB9H
14 13 12 11 10
0 0 0 0 0
Number of times of transfer
(when DBCn is written)
1024
1
2
3



1022
1023
CHAPTER 13 DMA CONTROLLER
After reset: 0000H
9 8 7 6 5
Remaining number of times of transfer
(when DBCn is read)
Completion of transfer or waiting for 1024 times of DMA transfer
Waiting for remaining one time of DMA transfer
Waiting for remaining two times of DMA transfer
Waiting for remaining three times of DMA transfer
Waiting for remaining 1022 times of DMA transfer
Waiting for remaining 1023 times of DMA transfer
R/W
DBC0L: FFFB6H
DBC1L: FFFB8H
4 3 2 1



0
552