Time Required For Switchover Of Cpu Clock And System Clock; Preconditions For Stopping Clock Oscillation - Renesas RL78/G1P Hardware User Manual

RL78/G1P

5.6.5 Time required for switchover of CPU clock and system clock

By setting bit 4 (MCM0) of the system clock control register (CKC), the main system clock can be switched (between
the high-speed on-chip oscillator clock and the high-speed system clock).
The actual switchover operation is not performed immediately after rewriting to the CKC register; operation continues
on the pre-switchover clock for several clocks (see Table 5-5 and Table 5-6).
Whether the main system clock is operating on the high-speed system clock or high-speed on-chip oscillator clock can
be ascertained using bit 5 (MCS) of the CKC register.
When the CPU clock is switched, the peripheral hardware clock is also switched.
Clock A
f
IH
Set Value Before Switchover
MCM0
0
(f = f )
MAIN IH
1
(f = f )
MAIN MX
Remarks 1. The number of clocks listed in Table 5-6 is the number of CPU clocks before switchover.
2. Calculate the number of clocks in Table 5-6 by removing the decimal portion.
Example When switching the main system clock from the high-speed system clock to the high-speed on-

5.6.6 Preconditions for stopping clock oscillation

The preconditions for stopping oscillation of the various clocks (and for disabling the external clock inputs) and the flag
settings to be made to stop oscillation of each clock or disable input of the given clock are listed in Table 5-7.
Before stopping the oscillation of a clock, check that the precondition for stopping clock oscillation is satisfied.
Table 5-7. Preconditions for Stopping Clock Oscillation and Flag Settings
Clock
High-speed on-chip
oscillator clock
X1 clock
External main system clock
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 5-5. Maximum Time Required for System Clock Switchover
Switching Directions
Table 5-6. Maximum Number of Clocks Required for f
f
f
MX IH
f <f
MX IH
f
f
MX IH
f <f
MX IH
chip oscillator clock (@ oscillation with f
= 2 (10/8) = 2.5  3 clocks
2f /f
MX IH
Precondition for Stopping Clock Oscillation
(or Disabling External Clock Input)
MCS = 1
(The CPU is operating on a clock other than the high-speed on-chip
oscillator clock.)
MCS = 0
(The CPU is operating on a clock other than the high-speed system clock.)
Clock B
f
MX
Set Value After Switchover
MCM0
0
(f = f )
MAIN IH
2f /f clock
MX IH
2 clock
= 8 MHz, f
IH
CHAPTER 5 CLOCK GENERATOR
Remark
See Table 5-6
 f
IH MX
1
(f = f )
MAIN MX
2 clock
2f /f clock
IH MX
= 10 MHz)
MX
Flag Settings of
CSC Register
HIOSTOP = 1
MSTOP = 1
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