Renesas RL78/G1P Hardware User Manual page 213

RL78/G1P
Figure 6-52. Operation Procedure When Input Pulse Interval Measurement Function Is Used
TAU
default
setting
Sets the TAUmEN bit of peripheral enable register 0
(PER0) to 1.
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 to CKm3.
Channel Sets timer mode register mn (TMRmn) (determines
default operation mode of channel).
setting
Sets the corresponding bit of the noise filter enable
register 1 (NFEN1) to 0 (off) or 1 (on).
Operation Sets TSmn bit to 1.
start The TSmn bit automatically returns to 0 because it is a
trigger bit.
Sets the corresponding bit of the noise filter enable
register 1 (NFEN1) to 0 (off) or 1 (on).
During Set values of only the CISmn1 and CISmn0 bits of the
operation TMRmn register can be changed.
The TDRmn register can always be read.
The TCRmn register can always be read.
The TSRmn register can always be read.
Set values of the TOMmn, TOLmn, TOmn, and TOEmn
bits cannot be changed.
Operation The TTmn bit is set to 1.
stop The TTmn bit automatically returns to 0 because it is a
trigger bit.
TAU The TAUmEN bit of the PER0 register is cleared to 0.
stop
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Software Operation
CHAPTER 6 TIMER ARRAY UNIT
Hardware Status
Input clock supply for timer array unit 0 is stopped.
(Clock supply is stopped and writing to each register is
disabled.)
Input clock supply for timer array unit 0 is supplied. Each
channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEmn = 1, and count operation starts.
Timer count register mn (TCRmn) is cleared to 0000H
at the count clock input.
When the MDmn0 bit of the TMRmn register is 1,
INTTMmn is generated.
Counter (TCRmn) counts up from 0000H. When the TImn
pin input valid edge is detected, the count value is
transferred (captured) to timer data register mn (TDRmn).
At the same time, the TCRmn register is cleared to
0000H, and the INTTMmn signal is generated.
If an overflow occurs at this time, the OVF bit of timer
status register mn (TSRmn) is set; if an overflow does not
occur, the OVF bit is cleared.
After that, the above operation is repeated.
TEmn = 0, and count operation stops.
The TCRmn register holds count value and stops.
The OVF bit of the TSRmn register is also held.
Input clock supply for timer array unit 0 is stopped.
All circuits are initialized and SFR of each channel is
also initialized.
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