RL78/G1P
Instruction
Mnemonic
Group
Rotate
ROR
A, 1
ROL
A, 1
RORC
A, 1
ROLC
A, 1
ROLWC
AX,1
BC,1
Bit
MOV1
CY, A.bit
manipulate
A.bit, CY
CY, PSW.bit
PSW.bit, CY
CY, saddr.bit
saddr.bit, CY
CY, sfr.bit
sfr.bit, CY
CY,[HL].bit
[HL].bit, CY
CY, ES:[HL].bit
ES:[HL].bit, CY
AND1
CY, A.bit
CY, PSW.bit
CY, saddr.bit
CY, sfr.bit
CY,[HL].bit
CY, ES:[HL].bit
OR1
CY, A.bit
CY, PSW.bit
CY, saddr.bit
CY, sfr.bit
CY, [HL].bit
CY, ES:[HL].bit
Notes 1.
Number of CPU clocks (f
when no data is accessed.
2.
Number of CPU clocks (f
Remark
Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 26-5. Operation List (14/18)
Operands
Bytes
Note 1 Note 2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
2
2
3
3
2
3
3
3
2
3
2
3
3
3
2
3
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the program memory area is accessed.
CLK
Clocks
A
1
(CY, A
, A
7
0
A
1
(CY, A
, A
0
7
(CY A
1
, A
0
7
(CY A
1
, A
7
0
(CY AX
1
, AX
15
(CY BC
1
, BC
15
CY A.bit
1
A.bit CY
1
CY PSW.bit
1
PSW.bit CY
4
CY (saddr).bit
1
(saddr).bit CY
2
CY sfr.bit
1
sfr.bit CY
2
CY (HL).bit
1
4
(HL).bit CY
2
CY (ES, HL).bit
2
5
(ES, HL).bit CY
3
CY CY A.bit
1
CY CY PSW.bit
1
CY CY (saddr).bit
1
CY CY sfr.bit
1
CY CY (HL).bit
1
4
CY CY (ES, HL).bit
2
5
CY CY A.bit
1
CYX CY PSW.bit
1
CY CY (saddr).bit
1
CY CY sfr.bit
1
CY CY (HL).bit
1
4
CY CY (ES, HL).bit
2
5
CHAPTER 26 INSTRUCTION SET
Operation
A
)×1
m-1
m
A
)×1
m+1
m
CY, A
A
)×1
m-1
m
CY, A
A
)×1
m+1
m
CY, AX
AX
) ×1
0
m+1
m
CY, BC
BC
) ×1
0
m+1
m
Flag
Z
AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
714