Renesas RL78/G1P Hardware User Manual page 272

RL78/G1P
(3) A/D conversion times for 8-bit A/D conversion when there is no power supply stabilization wait time
A/D Converter Mode Mode
Register 0 (ADM0)
FR2 FR1 FR0 LV0
0 0 0 0 Normal 1 f
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 1 Normal 2 f
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
When using ANI16, setting this value is prohibited.
Note
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (t
described in 27.6.1 A/D converter characteristics.
2. Rewrite the FR2 to FR0 and LV0 bits to other than the same data while conversion is stopped (ADCS =
0, ADCE = 0).
3. The above conversion time does not include clock frequency errors. Select conversion time, taking
clock frequency errors into consideration.
4. In software trigger mode and hardware trigger no-wait mode, make settings that affect the
conversion time such that the following conditions are satisfied.
 f
must be in the range from 1 to 16 MHz.
AD
 When the setting of the ADISS bit of the ADS register is 1, selecting the temperature sensor or
internal reference voltage output, the following condition applies.
Setting LV0 to 0 is prohibited.
Only setting LV0 to 1 is permitted.
Remark f : CPU/peripheral hardware clock frequency
CLK
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 9-3. A/D Conversion Time Selection (3/4)
(for software trigger mode and hardware trigger no-wait mode)
Conversion Number of
Clock (f ) Conversion
AD
Clock
(Number of
Sampling
Clock)
/32 41 f
CLK AD
(number of
sampling
f /16
CLK
clock:
f /8
11 f )
CLK
AD
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
f /1
CLK
/32 53 f
CLK AD
(number of
sampling
f /16
CLK
clock:
f /8
23 f )
CLK
AD
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
f /1
CLK
Conversion
Time
f = 1 f
CLK
MHz
1312/f Setting Setting
CLK
prohibited prohibited
656/f
CLK
328/f
CLK
246/f
CLK
205/f
CLK
164/f
41
CLK
82/f
20.5
CLK
Note

41/f
41 s 10.25
Note
CLK
Note
1696/f Setting Setting
CLK
prohibited prohibited
848/f
CLK
424/f
CLK
318/f
CLK
265/f
CLK
212/f
53
CLK
106/f
26.5
CLK
Note

53/f
53 s 13.25
Note
CLK
Note
CHAPTER 9 A/D CONVERTER
Selected Conversion Times
V = 2.7 to 3.6 V
DD
= 4 f = 8 f = 16
CLK CLK CLK
MHz MHz MHz
Setting Setting
prohibited prohibited

41 s
Note
 
41 s 20.5 s
Note
Note

30.75 s 15.375
Note Note

25.625 s 12.8125
Note Note
  
s 20.5 s 10.25
Note
Note Note
  
s 10.25 s 5.125
Note Note
 
s 5.125 s 2.5625
Note Note
Setting Setting
prohibited prohibited

53 s
 
53 s 26.5 s
Note

39.75 s 19.875
Note

33.125 s 16.5625
Note
  
s 26.5 s 13.25
Note
Note
  
s 13.25 s 6.625
Note
 
s 6.625 s 3.3125
Note
f = 32
CLK
MHz

41 s
Note

20.5 s
Note

10.25 s
Note
 
s 7.6875 s
Note
 
s 6.40625 s
Note

s 5.125 s
Note

s 2.5625 s
Note

Setting
s
prohibited

53 s

26.5 s

13.25 s
 
s 9.9375 s
 
s 8.28125 s

s 6.625 s

s 3.3125 s

s Setting
prohibited
)
CONV
253