Renesas RL78/G1P Hardware User Manual page 511

RL78/G1P
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKEn = 1)
Master
IICAn
SCLAn
Slave
IICAn
SCLAn
ACKEn
Transfer lines
SCLAn
SDAAn
Remark ACKEn: Bit 2 of IICA control register n0 (IICCTLn0)
WRELn: Bit 5 of IICA control register n0 (IICCTLn0)
A wait may be automatically generated depending on the setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0).
Normally, the receiving side cancels the wait state when bit 5 (WRELn) of the IICCTLn0 register is set to 1 or when
FFH is written to the IICA shift register n (IICAn), and the transmitting side cancels the wait state when data is written to
the IICAn register.
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STTn) of the IICCTLn0 register to 1
• By setting bit 0 (SPTn) of the IICCTLn0 register to 1
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-20. Wait (2/2)
Master and slave both wait
after output of ninth clock
6 7 8 9
H
6 7 8 9
D2 D1 D0 ACK
Generate according to previously set ACKEn value
CHAPTER 12 SERIAL INTERFACE IICA
IICAn data write (cancel wait)
1
Wait from
master and
Wait from slave
slave
1
D7
2 3
FFH is written to IICAn or WRELn is set to 1
2 3
D6 D5
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