Renesas RL78/G1P Hardware User Manual page 610

RL78/G1P
15.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt
request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed below.
 MOV PSW, #byte
 MOV PSW, A
 MOV1 PSW. bit, CY
 SET1 PSW. bit
 CLR1 PSW. bit
 RETB
 RETI
 POP PSW
 BTCLR PSW. bit, $addr20
 EI
 DI
 SKC
 SKNC
 SKZ
 SKNZ
 SKH
 SKNH
 Write instructions for the IF0L, IF0H, IF1L, IF2L, MK0L, MK0H, MK1L, MK2L, PR00L, PR00H, PR01L, PR02L,
PR10L, PR10H, PR11L, and PR12L registers
Figure 15-11 shows the timing at which interrupt requests are held pending.
CPU processing
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 15-11. Interrupt Request Hold
Instruction N Instruction M
CHAPTER 15 INTERRUPT FUNCTIONS
PSW and PC saved, jump
to interrupt servicing
Interrupt servicing
program
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