Renesas RL78/G1P Hardware User Manual page 658

16-bit single-chip microcontroller
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RL78/G1P
Notes 1.
The LVIMK flag is set to "1" by reset signal generation.
2.
After an interrupt is generated, perform the processing according to Figure 19-7 Processing Procedure
After an Interrupt Is Generated in interrupt and reset mode.
3.
After a reset is released, perform the processing according to Figure 19-8 Initial Setting of Interrupt and
Reset Mode in interrupt and reset mode.
Remark V
: POR power supply rise detection voltage
POR
V
: POR power supply fall detection voltage
PDR
Internal reset by LVD is
generated
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 19-7. Processing Procedure After an Interrupt Is Generated
INTLVI generated
Save processing
LVISEN = 1
LVILV = 0
LVISEN = 0
No
LVIOMSK = 0
Yes
Yes
LVD reset generated
No
LVISEN = 1
LVIMD = 0
LVISEN = 0
Normal operation
CHAPTER 19 VOLTAGE DETECTOR
Perform required save processing.
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1).
Set the LVILV bit to 0 to set the high-voltage detection
level (VLVDH).
Set the LVISEN bit to 0 to enable voltage detection.
The MCU returns to normal operation when internal
reset by voltage detector (LVD) is not generated,
since a condition of V
becomes V
DD
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1)
Set the LVIMD bit to 0 to set interrupt mode.
Set the LVISEN bit to 0 to enable voltage detection.
 V
.
DD
LVDH
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