Renesas RL78/G1P Hardware User Manual page 661

RL78/G1P
(2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released
There is some delay from the time supply voltage (V
been generated.
In the same way, there is also some delay from the time LVD detection voltage (V
time LVD reset has been released (see Figure 19-10).
Figure 19-10. Delay from the time LVD reset source is generated until the time LVD reset has been generated or released
Supply voltage (V )
DD
V
LVD
LVD reset signal
<1>: Detection delay (300
(3) However, when the operating voltage falls while interrupt mode is set, enter STOP mode, or enable the reset status
using the external reset pin before the voltage falls below the operating voltage range shown in 27.4 AC
Characteristics. When restarting operation, confirm that the supply voltage has returned to the operating voltage
range.
(4) When the LVD is off, it is necessary to perform an external reset. For an external reset, input a low level for 10 s or
____________
more to the RESET
before power-on, keep the low level for at least 10 s during the period in which the supply voltage is within the
operating voltage range shown in 27.4 AC Characteristics, and then input a high level. After power is applied, do not
input a high level to the RESET
shown in 27.4 AC Characteristics.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
<1>

s (MAX.))
pin. To perform an external reset when power is applied, input a low level to the RESET
____________
pin during a period in which the supply voltage is not within the operating range
CHAPTER 19 VOLTAGE DETECTOR
) < LVD detection voltage (V
DD
) until the time LVD reset has
LVD
)  supply voltage (V
LVD DD
Time
<1>
____________
) until the
pin
642