Renesas RL78/G1P Hardware User Manual page 238

RL78/G1P
Figure 6-71. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs)
Master channel
(interval timer mode)
CKm1
Operation clock
CKm0
TSmn
Slave channel 1
(one-count mode)
CKm1
Operation clock
CKm0
Slave channel 2
(one-count mode)
CKm1
Operation clock
CKm0
m: Unit number (m = 0), n: Master channel number (n = 0, 2)
Remark
p: Slave channel number 1, q: Slave channel number 2
n < p < q  3 (Where p and q are integers greater than n)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 6 TIMER ARRAY UNIT
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Timer counter
register mp (TCRmp)
Timer data
register mp (TDRmp)
Timer counter
register mq (TCRmq)
Timer data
register mq (TDRmq)
Interrupt
Interrupt signal
controller
(INTTMmn)
Output
TOmp pin
controller
Interrupt
Interrupt signal
controller
(INTTMmp)
Output
TOmq pin
controller
Interrupt
Interrupt signal
controller
(INTTMmq)
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