Renesas RL78/G1P Hardware User Manual page 127

RL78/G1P
Address: F00F0H
Symbol 7
PER0 0
SAU0EN
0
1
TAU0EN
0
1
Caution Be sure to clear bits 1, 3 and 7 to "0".
Address: F007AH
Symbol <7>
PER1 DACEN
DACEN
0
1
Caution Be sure to clear bits 0 to 6 to "0".
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2)
After reset: 00H R/W
<6> <5>
IICA1EN ADCEN
Stops input clock supply.
 SFR used by the serial array unit 0 cannot be written.
 The serial array unit 0 is in the reset status.
Enables input clock supply.
 SFR used by the serial array unit 0 can be read and written.
Stops input clock supply.
 SFR used by timer array unit 0 cannot be written.
 Timer array unit 0 is in the reset status.
Enables input clock supply.
 SFR used by timer array unit 0 can be read and written.
Figure 5-8. Format of Peripheral Enable Register 1 (PER1)
After reset: 00H R/W
6 5
0 0
Stops input clock supply.
 SFR used by the D/A converter cannot be written.
 The D/A converter is in the reset status.
Enables input clock supply.
 SFR used by the D/A converter can be read and written.
<4> 3
IICA0EN 0
Control of serial array unit 0 input clock supply
Control of timer array unit 0 input clock supply
4 3
0 0
Control of D/A converter input clock supply
CHAPTER 5 CLOCK GENERATOR
<2> 1
SAU0EN 0
1 1
0 0
<0>
TAU0EN
0
0
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