Renesas RL78/G1P Hardware User Manual page 587

RL78/G1P
13.6 Cautions on Using DMA Controller
(1) Priority of DMA
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending
DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated
at the same time, however, their priority are DMA channel 0 > DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence,
and then interrupt servicing is executed.
(2) DMA response time
The response time of DMA transfer is as follows.
Response time
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
Remark
(3) Operation in standby mode
The DMA controller operates as follows in the standby mode.
Status
HALT mode
STOP mode
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 13-3. Response Time of DMA Transfer
3 clocks
transfer.
2. When executing a DMA pending instruction (see 13.6 (4)), the maximum response
time is extended by the execution time of that instruction to be held pending.
3. Do not specify successive transfer triggers for a channel within a period equal to the
maximum response time plus one clock cycle, because they might be ignored.
1 clock: 1/f (f : CPU clock)
CLK CLK
Table 13-4. DMA Operation in Standby Mode
Normal operation
Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
Minimum Time
10 clocks
DMA Operation
CHAPTER 13 DMA CONTROLLER
Maximum Time
Note
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