External Clock Input; Pll Circuit; Frequency Divider; Figure 18.4 External Clock Input (Examples) - Renesas H8SX/1520 Series Hardware Manual

Section 18 Clock Pulse Generator

Table 18.2 Crystal Resonator Characteristics

Frequency (MHz)
R Max. (Ω)
S
C Max. (pF)
0
18.2.2

External Clock Input

An external clock signal can be input as shown in the examples in figure 18.4. If the XTAL pin is
left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is
input to the XTAL pin, make sure that the external clock is held high in standby mode.
For the input conditions of the external clock, refer to table 21.4, Clock Timing, in section 21.3.1,
Clock Timing. The input external clock should be from 4 to 9 MHz.
18.3

PLL Circuit

The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 8. The frequency multiplication factor is fixed.
18.4

Frequency Divider

The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After bits ICK2
to ICK0 and PCK 2 to PCK0 are modified, this LSI operates at the modified frequency.
Rev. 3.00 Mar. 14, 2006 Page 666 of 804
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4 6
120 100
7 7
EXTAL
XTAL
(a) XTAL pin left open
EXTAL
XTAL
(b) Counter clock input on XTAL pin

Figure 18.4 External Clock Input (Examples)

8
80
7
External clock input
Open
External clock input
9
80
7