C Bus Interrupt Enable Register (Icier) - Renesas H8 Series Hardware Manual

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Section 15 I C Bus Interface 2 (IIC2)
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15.3.4 I

C Bus Interrupt Enable Register (ICIER)

ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Bit Bit Name Initial Value R/W Description
7 TIE 0
6 TEIE 0
5 RIE 0
Rev. 3.00 Sep. 14, 2006 Page 248 of 408
REJ09B0105-0300
R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
R/W Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt (TEI) at
the rising of the ninth clock while the TDRE bit in ICSR is 1.
TEI can be canceled by clearing the TEND bit or the TEIE bit
to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
R/W Receive Interrupt Enable
This bit enables or disables the receive data full interrupt
request (RXI) and the overrun error interrupt request (ERI)
with the clocked synchronous format, when a receive data is
transferred from ICDRS to ICDRR and the RDRF bit in ICSR
is set to 1. RXI can be canceled by clearing the RDRF or RIE
bit to 0.
0: Receive data full interrupt request (RXI) and overrun error
interrupt request (ERI) with the clocked synchronous
format are disabled.
1: Receive data full interrupt request (RXI) and overrun error
interrupt request (ERI) with the clocked synchronous
format are enabled.