Figure 11.18 Contention Between Compare Register Write And Compare Match - Renesas H8S Series Hardware Manual

Contention between Compare Register Write and Compare Match: If a compare match
occurs in the T state of a compare register (TGR or TPDR) write cycle, the compare register write
3
is not performed, and data is transferred from the buffer register (TBRU, TBRV, TBRW, or
TPBR) to the compare register by a buffer operation.
Figure 11.18 shows the timing in this case.
φ
Address
Write signal
Compare match
signal
TGI interrupt
Buffer register
Compare register

Figure 11.18 Contention between Compare Register Write and Compare Match

Section 11 Motor Management Timer (MMT)
Compare register
write cycle
T T T
1 2 3
Compare register address
N
N
Compare register
write data
Rev. 6.00 Mar 15, 2006 page 271 of 570
REJ09B0211-0600