Usage Notes; Kbioe Setting And Kclk Falling Edge Detection - Renesas H8S/2100 Series Hardware Manual

19.5

Usage Notes

19.5.1

KBIOE Setting and KCLK Falling Edge Detection

When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the
KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the
KCLK falling edge is detected.
If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 19.19 shows the
timing of KBIOE setting and KCLK falling edge detection.
φ
KCLK (pin)
Internal KCLK
(KCLKI)
KBIOE
Falling edge
signal
KBFSEL
KBE
KBF
Figure 19.19 KBIOE Setting and KCLK Falling Edge Detection Timing
T1 T2
Section 19 Keyboard Buffer Control Unit (PS2)
Rev. 1.00 Apr. 28, 2008 Page 613 of 994
REJ09B0452-0100