Figure 7.29 Example Of Transfer In Normal Transfer Mode Activated By Dreq Falling Edge - Renesas H8SX/1500 Series Hardware Manual

Activation Timing by DREQ Falling Edge
(4)
Figure 7.29 shows an example of normal transfer mode activated by the DREQ signal falling edge.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If
a high level of the DREQ signal has been detected until completion of the DMA write cycle,
receiving the next transfer request resumes and then a low level of the DREQ signal is detected.
This operation is repeated until the transfer is completed.
Bus released
Bφ
DREQ
Address bus
DMA
Wait
operation
Request
Channel
Min. of 3 cycles
[1]
[2]
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
[1]
request is held.
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the Bφ signal is started to detect a high level of the
DREQ signal.
[4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Figure 7.29 Example of Transfer in Normal Transfer Mode Activated
DMA read DMA write
cycle cycle
Transfer source Transfer destination
Write
Read Wait
Duration of transfer
request disabled
[3] [4]
Transfer request enable resumed
by DREQ Falling Edge
Section 7 DMA Controller (DMAC)
DMA read
Bus released
cycle
Transfer source
Write
Read
Duration of transfer
Request
request disabled
Min. of 3 cycles
[5] [6]
Rev. 3.00 Mar. 14, 2006 Page 187 of 804
DMA write
Bus released
cycle
Transfer destination
Wait
[7]
Transfer request enable resumed
REJ09B0104-0300