Bus Cycles In Dual Address Mode; Figure 7.24 Example Of Transfer In Normal Transfer Mode By Cycle Stealing - Renesas H8SX/1500 Series Hardware Manual

7.4.10

Bus Cycles in Dual Address Mode

(1)
Normal Transfer Mode (Cycle Stealing Mode)
In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one
word, or one longword) is completed. One bus cycle or more by the CPU are executed in the bus
released cycles.
In figure 7.24, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer
mode by cycle stealing.
DMA read
cycle
Bφ
Address bus
RD
LHWR, LLWR
TEND
Bus
released

Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing

In figures 7.25 and 7.26, the TEND signal output is enabled and data is transferred in longwords
from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal
transfer mode by cycle stealing.
In figure 7.25, the transfer source (DSAR) is not aligned with a longword boundary and the
transfer destination (DDAR) is aligned with a longword boundary.
In figure 7.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer
destination (DDAR) is not aligned with a longword boundary.
DMA read
DMA write
cycle
cycle
Bus
released
Section 7 DMA Controller (DMAC)
DMA write DMA read
cycle cycle
Bus
Last transfer cycle
released
Rev. 3.00 Mar. 14, 2006 Page 183 of 804
DMA write
cycle
Bus
released
REJ09B0104-0300