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8.5.9
Basic DMAC Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 8-18. In this example, word-
size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller
settings.
CPU cycle
Address bus
HWR
LWR
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
DMAC cycle (1-word transfer)
T
T
T
1
2
1
ø
Source
address
RD
Figure 8-18 Example of DMA Transfer Bus Timing
T
T
T
T
T
2
3
1
2
3
Destination address
CPU cycle
301
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