Vsb Read/Write Timing Example; Vsb Timing Example - Renesas NU85E Preliminary User's Manual

4.9.4 VSB read/write timing example

The read/write timing example of SRAM connected to the NT85E500 is shown below.
VBCLK (Input)
VMTTYP1, VMTTYP0 (Output)
VMA27 to VMA0 (Output)
VBDI31 to VBDI0 (Input)
VBDO31 to VBDO0 (Output)
VMSTZ (Output)
VMWRITE (Output)
VMBENZ3 to VMBENZ0 (Output)
VMCTYP2 to VMCTYP0 (Output)
VMSIZE1, VMSIZE0 (Output)
VMSEQ2 to VMSEQ0 (Output)
VMWAIT (Input)
VMAHLD (Input) L
VMLAST (Input) L
VBDC (Output)
VBDV (Output)
VDCSZ7 to VDCSZ0 (Output)
DI31 to DI0 (Input)
Note
DO31 to DO0 (Output) Note
RDZ (Output) Note
WRZ3 to WRZ0 (Output)
Note
Note NT85E500 signal
Remark O mark: Sampling timing
CHAPTER 4 BCU
Figure 4-15. VSB Timing Example (1/2)
(a) VSB read timing example
Read
(1,0) (1,1)
A.0
D.0
(0,0,0,0)
(0,0,1)
(1,0)
xxH
D.0
Preliminary User's Manual A14874EJ3V0UM
Read
(0,0) (1,0)
0000000H A.1
00000000H
(1,1,1,1) (0,0,0,0)
(0,0,0) (0,0,1)
(0,0) (1,0)
(0,0,0)
FFH xxH
00000000H
(1,1,1,1)
(1,1)
D.1
D.1
111