Figure 25.18 Mpx-Io Interface Bus Cycle (Three Address Cycles, One Software Wait Cycle, One External Wait Cycle) - Renesas HD6417641 Hardware Manual

Section 25 Electrical Characteristics
CKIO
A25 to A0
CS5B
RD/WR
t
AH
RD
D15 to D0
WE1 to WE0
D15 to D0
BS
WAIT
DACKn*
Note: * Waveform for DACKn when active low is selected.
(Three Address Cycles, One Software Wait Cycle, One External Wait Cycle)
Rev. 4.00 Sep. 14, 2005 Page 930 of 982
REJ09B0023-0400
Ta1 Ta2
t
AD1
t
CSD1
t
RWD1
t t
AHD AHD AHD
t
MAD
t
MAD
t t
BSD BSD
t
DACD
Figure 25.18 MPX-IO Interface Bus Cycle
Ta3 T1
t
RSD
t
MAH
Address
t
WED1
t
WDD1
t
MAH
Address
t
WTH1
t
Tw Tw T2
t
RSD
t
RDS1
Data
t
WED1
Data
t
WTH1
t
WTS1 WTS1
t
AD1
t
CSD1
t
RWD1
t
RDH1
t
WDH1
t
DACD