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S3C6400X RISC MICROPROCESSOR
Figure 38-3 shows FIR demodulation state machine. The state machine starts when ACR register bit 6 is
set to logic high. The incoming data will be depacketized by removing preamble and start flag and stop
flag.
Figure 38-3 FIR demodulation process
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IRDA
38-7
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